The Hybrid Field - Programmable Architecture HYBRID FPGA

capacity field-programmable devices have enjoyed a rapidly expanding market and have become widely accepted for the implementation of small to moderately large digital circuits. The two main types of FPDs, field-programmable gate arrays and complex programmable logic devices, are both widely used, each offering particular strengths. FPGAs programmed with static RAM technology are usually based on lookup tables. Their main strengths are very high logic capacity—in the range of hundreds of thousands of equivalent logic gates—and good speed-performance—up to 50-MHz system clock rates. On the other hand, CPLDs consist of multiple PLA-like blocks, in which the OR planes are partly fixed. Their characteristics include medium capacity, in the range of a few thousand gates, and ultrahigh speedperformance, sometimes in excess of a 200MHz system clock rate. In this article, we propose a new FPD architecture, called the Hybrid FieldProgrammable Architecture, which combines FPGAs and CPLDs. The basis of the HFPA is that some parts of digital circuits are well-suited for implementation with LUTs, but other parts benefit more from the productterm-based structures in CPLDs. Comparison with an architecture containing only LUTs indicates that the new architecture offers significant savings in total chip area. Also, the HFPA can reduce the depth of circuits implemented in the FPGA, which may provide improvements in speed-performance.